Since the introduction of the first personal computer (“PC”), technological advances to make PCs more useful have continued at an amazing rate. Microprocessors that control PCs have become faster and faster, with operational speeds eclipsing the gigahertz (one billion operations per second) and continuing well beyond.
Productivity has also increased tremendously because of the explosion in development of software applications. In the early days of the PC, people who could write their own programs were practically the only ones who could make productive use of their computers. Today, there are thousands of software applications ranging from games to word processors and from voice recognition to web browsers.
Not surprisingly, the increasing complexity of computers and software applications has presented technologists with some challenging obstacles along the way. One such obstacle is the continual increase in the amount of computing power needed to run increasingly large and complex software applications. Increased computing power is also needed to enable networked computer systems to provide services such as file and printer sharing to larger numbers of users in a cost effective manner.
One way to increase computing power has been to design computer systems that are capable of processing data faster. Computers may use clock signals to synchronize the processing of data. Bits of data in the form of electrical signals that represent “0s” and “1s” (logical lows and highs) may be clocked into integrated circuit devices, which may process the 0s and 1s to do useful work. Data signals may be passed through a data buffer circuit before being latched and stored in a device known as a register, which may also be known as a latch or flip-flop. A clock signal, which may be an electrical signal in the form of a square wave, may be used to latch data bits into the register. Registers are incorporated into an integrated circuit device to receive data bits and hold them for further processing by the internal workings of the integrated circuit device. The registers may be designed to receive a new data bit with each rising edge (or falling edge) of the clock signal. A rising edge of the clock occurs when the clock signal transitions from a relatively low level to a relatively high level. A falling clock edge occurs when the clock signal transitions from a relatively high level to a relatively low level.
If the speed of the clock is increased, data is processed at a faster rate, with a corresponding increase in computing power. For example, if data bits are being clocked into data buffers for further processing on each rising edge of a system clock, twice as much data may be clocked into the registers if the clock rate is doubled. A potential problem may arise, however, because, as clock speed increases, there is less time during each clock cycle to perform work.
One problem faced by designers of input buffer circuits as clock speeds increase is insufficient data setup time. Setup time refers to the length of time that a data signal should be stable to guarantee that it will be clocked into an input register by the relevant edge of a clock signal. Setup time is potentially a problem because electrical data signals transition rapidly and may take time to settle after a transition (for example a transition from a logical “0” to a logical “1” and vice versa). As clock speeds get faster, the time in which data signals have to stabilize or settle gets shorter. If a data signal is not stable when the relevant clock edge latches the signal into a register, the signal may be incorrectly interpreted. For example, a logical “0” may be mistakenly latched into the register as a logical “1” or vice versa. If data is incorrectly latched into a register, the performance of the computer system is degraded.
Another factor that may affect the clocking of data into a register is the synchronization of the clock signal across multiple data inputs. In many integrated circuit devices, multiple data bits may be clocked in parallel into their respective registers by a single clock signal. Many factors may introduce small variations into the synchronization of the clock signal with respect to when each of the multiple data bits is latched into its register. One factor may be a difference in length that the clock signal has to travel to actuate the registers of different data inputs. Another factor may be that the registers that receive the data have differing voltages at which they are actuated by the clock signal. These differences may result from variations in integrated circuit processing or temperature, among others. A system that may reduce the effects of these variations may be desirable.